Half Adder & Full Adder

Half adder

CHIP HalfAdder {

IN a, b;

OUT sum, // LSB of a + b

carry; // MSB of a + b

PARTS:

Xor(a=a, b=b, out=sum);
And(a=a, b=b, out=carry);
}


Full Adder

CHIP FullAdder {
IN a, b, c;

OUT sum, // LSB of a + b + c

carry; // MSB of a + b + c

PARTS:

HalfAdder(a=c, b=b, sum=sum1, carry=carry1);
HalfAdder(a=a, b=sum1, sum=sum);
And(a=a, b=sum1, out=out1);
Or(a=carry1, b=out1, out=carry);

}


Adder 16 bit

CHIP Add16 {


IN a[16], b[16];

OUT out[16];


PARTS:

HalfAdder(a= a[0], b=b[0], sum= out[0], carry=carry1);
FullAdder(a= a[1], b=b[1], c =carry1, sum = out[1], carry = carry2);
FullAdder(a= a[2], b=b[2], c =carry2, sum = out[2], carry = carry3);
FullAdder(a= a[3], b=b[3], c =carry3, sum = out[3], carry = carry4);
FullAdder(a= a[4], b=b[4], c =carry4, sum = out[4], carry = carry5);
FullAdder(a= a[5], b=b[5], c =carry5, sum = out[5], carry = carry6);
FullAdder(a= a[6], b=b[6], c =carry6, sum = out[6], carry = carry7);
FullAdder(a= a[7], b=b[7], c =carry7, sum = out[7], carry = carry8);
FullAdder(a= a[8], b=b[8], c =carry8, sum = out[8], carry = carry9);
FullAdder(a= a[9], b=b[9], c =carry9, sum = out[9], carry = carry10);
FullAdder(a= a[10], b=b[10], c =carry10, sum = out[10], carry = carry11);
FullAdder(a= a[11], b=b[11], c =carry11, sum = out[11], carry = carry12);
FullAdder(a= a[12], b=b[12], c =carry12, sum = out[12], carry = carry13);
FullAdder(a= a[13], b=b[13], c =carry13, sum = out[13], carry = carry14);
FullAdder(a= a[14], b=b[14], c =carry14, sum = out[14], carry = carry15);
FullAdder(a= a[15], b=b[15], c =carry15, sum = out[15], carry = carry16);

}

Increment 16bit

CHIP Inc16 {

IN in[16];
OUT out[16];

PARTS:
Add16(a[0..15] = in[0..15], b[1..15] = false, b[0] = true, out = out);
}

All chips in the CHAPTER 1

Finally completed the Chapter1 project. Solutions are there in the below link

Chapter.1 solutions

CHAPTER 1

Chip Design is as interesting as Programming. For building OR gate from NAND,we need to remember the basic theorems in Digital electronics.De_Morgan laws



DMUX


MUX





DMux4Way



CHIP DMux4Way {

IN in, sel[2];

OUT a, b, c, d;

PARTS:


DMux(in=in, sel=sel[1], a=mux1, b=mux2);

DMux(in=mux1, sel=sel[0], a=a, b=b);

DMux(in=mux2, sel=sel[0], a=c, b=d);

}




DMux8Way

CHIP DMux8Way {

IN in, sel[3];

OUT a, b, c, d, e, f, g, h;

PARTS:

DMux(in=in, sel=sel[2], a=mux1, b=mux2);
DMux4Way(in=mux1, sel[0]=sel[0], sel[1]=sel[1], a=a,b=b,c=c,d=d);
DMux4Way(in=mux2, sel[0]=sel[0], sel[1]=sel[1], a=e,b=f,c=g,d=h);

}

AND16 chip

built the AND16

This is the second chip tested successfully

Building all the chips

First chip AND built from NAND gate. The first chapter project is to build all the chips from NAND gate.One who finish the first chapter should build all the chips from NAND and test it.



reference link http://www1.idc.ac.il/tecs/plan.html

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